1. Field of the Invention
The present invention relates to direct conversion receivers and, more particularly, to a direct conversion receiver configured to attenuate a DC offset in a signal band which occurs in a baseband signal processing block.
2. Description of Prior Art
As a method for canceling a DC offset in a direct conversion receiver, a method by means of high-pass filters employing capacitance elements 401 is known. Circuitry configured in accordance with this method is shown in FIG. 4. In this circuitry, because a part of a signal band is cut by the high-pass filters and these results in degraded signals, the cut-off frequency of the high-pass filters is required to be as small as possible.
If the amplification section of a receiver is configured to include multiple stages of gain control amplifiers 104, there is a possibility that the DC offset is over-amplified and saturated. Thus, capacitance elements are often employed between each stage of gain control amplifier. For example, this configuration is described in Harald Pretl et al., “Circuit and System Considerations for UMTS Zero-IF Receivers in SiGe BiCMOS,” MWE2001 Microwave Workshop Digest WS11-4, pp. 264-268.
In another example, DC offset cancellation means are separately attached to all gain control amplifiers in an analog baseband signal processing block. This circuitry is shown in FIG. 5. For example, a direct conversion receiver using such circuitry has been disclosed in Japanese Published Unexamined Patent Application No. 2001-211098. In this direct conversion receiver, each amplification stage in the analog baseband block is configured such that an analog to digital converter (ADC) is connected to the output of each gain control amplifier, a DC offset voltage generated is detected by a control element CTL, and a digital to analog converter (DAC) applies a voltage to cancel the detected DC offset voltage to the gain control amplifier 104. In this arrangement, to use the direct conversion receiver in a Time Division Multiple Access (TDMA) system and a Time Division Duplex (TDD) system, the DC offset cancellation operation must be performed within an intermittent time period.